The present invention relates to an analog signal control method, an analog signal controller, and an AGC.
In recent years, analog signals are controlled by digital signals. Data read from a recording medium, for example, a magnetic disk is an analog signal which is converted to a digital signal. An amplification ratio of GCA (gain control amplifier) is calculated from the digital signal. The calculated amplification ratio is fed back to control the amplitude of the analog signal. The feedback loop is repeated to control the amplitude of the analog signal to be constant. In this event, since processing time (control delay: latency) on a calculating path for the digital processing affects the controllability of the analog signal, improved digital processing is required.
FIG. 1 is a schematic block diagram illustrating the configuration of a conventional analog signal controller 111. The analog signal controller 111 includes an analog control circuit 112, an A/D converter circuit (hereinafter referred to as ADC) 113, and a digital arithmetic circuit 114.
The analog signal controller 111 receives an analog input signal IN which is data read, for example, from a recording medium. After performing predetermined processing on the analog input signal IN, the analog signal controller 111 supplies the processed signal to a next circuit 115. The ADC 113 and the digital arithmetic circuit 114 operate in accordance with a clock signal CLK supplied from a PLL circuit, not shown.
The analog control circuit 112 processes the analog input signal IN in accordance with a control signal S31 to generate an analog processed signal S32. The analog control circuit 112 receives the control signal S31 from the digital arithmetic circuit 114. The analog processed signal S32 is supplied to the ADC 113 and the next circuit 115.
The ADC 113 converts the analog processed signal S32 to a digital signal S33 which is supplied to the digital arithmetic circuit 114.
The digital arithmetic circuit 114 executes various forms of calculation processing in accordance with the digital signal S33 to generate the control signal S31. The digital arithmetic circuit 114 feeds back the control signal S31 to the analog control circuit 112.
The analog signal controller 111 generates the control signal S31 in accordance with the analog processed signal S32, and controls the analog input signal IN in accordance with the control signal S31 in a feedback manner.
However, the analog signal controller 111 experiences a control delay (latency) caused by a control loop (comprised of the ADC 113 and digital arithmetic circuit 114) for controlling the analog input signal IN.
FIG. 2 is a block diagram of an automatic gain controller (hereinafter referred to as AGC), for example, in which the conventional analog signal controller 111 is embodied. The AGC 121 includes a gain control amplifier (hereinafter referred to as GCA) 112, a low pass filter (hereinafter referred to as LPF) 123, an ADC 124, an error calculating circuit 125, and a D/A converter circuit (hereinafter referred to as DAC) 126. The ADC 124 and the error calculating circuit 125 operate in accordance with a clock signal CLK supplied from a PLL circuit.
The GCA 122 receives an analog input signal IN. The GCA 122 amplifies the analog input signal IN with a predetermined gain in accordance with a control signal S41 to generate an analog amplified signal S42. The analog amplified signal S42 is supplied to the LPF 123.
The LPF 123 removes high frequency components from the analog amplified signal S42 amplified by the GCA 122 to generate an analog signal S43. The analog signal S43 is supplied to the ADC 124. The ADC 124 converts the analog signal S43 to a digital signal S44 which is supplied to the error calculating circuit 125.
The error calculating circuit 125 compares the digital signal S44 with a predetermined target value, and integrates its error components to generate an error digital signal S45 which is supplied to the DAC 126. The GCA 122 amplifies the analog input signal IN such that the target value causes the amplitude of the analog signal S43 to substantially cover a full input range of the ADC 124.
The DAC 126 converts the error digital signal S45 to an analog signal to generate the control signal S41 which is fed back to the GCA 122.
FIG. 3 is a block diagram illustrating the specific configuration of the error calculating circuit 125. The error calculating circuit 125 includes first to third calculating circuits 131 to 133, and first to third flip-flops (hereinafter referred to as FFs) 134 to 136.
The first calculating circuit 131 is an arithmetic circuit which takes an absolute value of the digital signal S44 and outputs the absolute digital signal. The first FF 134 latches the output signal of the first calculating circuit 131 in response to a clock signal CLK to generate a first latch signal D1. The first latch signal D1 is supplied to the second calculating circuit 132.
The second calculating circuit 132 calculates an error component between a target value previously stored in a register (not shown) and the first latch signal D1 to generate an error signal D2 in accordance with the result of the calculation. The error signal D2 is supplied to the second FF 135. The second FF 135 latches the error signal D2 in response to the clock signal CLK to generate a second latch signal A. The second latch signal A is supplied to the third calculating circuit 133.
The third calculating circuit 133 integrates the second latch signal A to generate an integration signal S. The integration signal S is fed back to the input side of the third calculating circuit 133. The third FF 136 latches the integration signal S in response to the clock signal CLK to generate an error digital signal S45. The error digital signal S45 is supplied to the DAC 126.
The AGC 121 optimizes the gain of the GCA 122 by a control loop which feeds back the control signal S41 in accordance with the analog amplified signal S42. The AGC 121 supplies the digital signal S44 to a next digital circuit.
However, in the AGC 121, a processing time taken by the ADC 124 and the error calculating circuit 125 in the control loop causes a latency for the analog input signal IN.
The error calculating circuit 125 is provided with the first to third FFs 134 to 136 at the input and output stages of the second and third calculating circuits 132, 133 (see FIG. 3) for increasing the calculating speed of these circuits. A latency occurring in the error calculating circuit due to the first to third FFs 134 to 136 at three stages corresponds to three clock pulses of the clock signal CLK, and particularly, the error calculating circuit 125 is significantly affected by the latency.
For example, as illustrated in FIG. 4, the analog input signal IN is sampled at time T1, and the GCA 122 is supplied at time T2 with the control signal S41 which is generated from a digital signal having a sampling value through the ADC 124 and the error calculating circuit 125. The control signal S41 generated from the analog input signal IN at time T1 acts on the analog input signal IN at time T2.
A difference between the times T1, T2 (=T2−T1) indicates the processing time taken by the ADC 124 and error calculating circuit 125, i.e., the control delay (latency). The control signal S41 supplied at time T2 is not suitable for the analog input signal IN at that time. Although the control signal S41 includes a calculated value based on a difference between the value of the analog input signal IN at time T1 and a target value, it does not include any calculated value based on a difference between the value of the analog input signal IN at time T2 and the target value. Therefore, the error calculating circuit suffers from low accuracy for analog signal control, and a long time for convergence of the amplitude of the analog input signal IN to a fixed value.